1. Field of the Invention
This invention relates to a semiconductor device including n-channel and p-channel MOS field effect transistors each having offset spacers or gate sidewall films on either side of a gate electrode and a method of manufacturing the same.
2. Description of the Related Art
In conventional MOS field effect transistors, an offset spacer or a gate sidewall film is formed on either side of a gate electrode. In order to configure such MOS field effect transistors, the same process is used for manufacturing both an n-channel MOS field effect transistor (hereinafter referred to as nMOSFET) and a p-channel MOS field effect transistor (hereinafter referred to as pMOSFET) on the same substrate, as shown in FIGS. 1 to 5. This process will be described below.
Gate electrodes 101A and 101B are formed and then a film 102 is deposited to serve as an offset spacer (see FIG. 1). Then, the film 102 is processed to form offset spacers 102A and 102B on either side of the gate electrodes 101A and 101B, respectively (see FIGS. 1 and 2). Impurities are ion-implanted into the resultant structure to form extension regions 103A and 103B with each of transistor regions masked by a resist film alternatively (see FIG. 3).
Then, a film 104 is deposited on the resultant structure to serve as a gate sidewall film (see FIG. 4). Subsequently, the film 104 is processed to form a gate sidewall films 104A and 104B on the side of the offset spacers 102A and 102B, respectively. Moreover, impurities are ion-implanted to form source/drain regions 105A under protection of rest of the transistor regions, then source/drain regions 105B are formed similarly (see FIG. 5).
Since the same process is used as described above, the offset spacers 102A and 102B of the same thickness or the gate sidewall films 104A and 104B of the same thickness are formed in both nMOSFETs and pMOSFETs. It is however understood that the optimum thickness of the offset spacer varies between the nMOSFETs and pMOSFETs in these days of the progress of miniaturization of semiconductor devices. It is thus difficult to make each of the nMOSFETs and pMOSFETs in predetermined characteristics when their offset spacers have the same thickness.
If a process from deposition to etching of a film serving as offset spacers is performed only once, their thicknesses are the same. However, if the process is done two times, effective offset spacers of different thicknesses can be formed. More specifically, first, a first offset spacers are formed on either side of each of the gate electrodes of the nMOSFET and pMOSFET. Then, an extension region is formed in one of the MOSFETs. Next second offset spacers are formed on the first offset spacers. After that, another extension region is formed in the other MOSFET. Through the above process, the effective offset spacers can be varied in thickness between the nMOSFET and pMOSFET (see, for example, K. Ohta and H. Nakaoka, “Double Offset Implantation Technique for High Performance 80 nm CMOSFET With Low Gate Leakage Current”, SEMI Forum Japan 2002, ULSI Technology Seminar, Section 4, pp. 42-47).
A process of forming offset spacers of effectively different thicknesses as described above will be described with reference to the drawings.
First offset spacers 102A and 102B are formed on the sides of gate electrodes 101A and 101B, respectively. Then, impurities are ion-implanted into the resultant structure with one of transistor regions to form an extension region 107 by protecting with a resist film 106 on the other transistor region (see FIG. 6).
The resist film 106 is removed from the resultant structure and a film 108, serving as a second offset spacer, is deposited on the structure (see FIG. 7). Then, the film 108 is processed and second offset spacers 108A and 108B are formed on the sides of the first offset spacers 102A and 102B, respectively. After that, an extension region 109 is formed in one transistor region by ion-implanting impurities into the resultant structure while the other transistor region whose polarity is opposite to that of the transistor region in the first ion implantation is being protected by the resist film (see FIG. 8).
In the foregoing process, however, the deposition of a film serving as offset spacers has to be performed two times. Therefore, the variations in the thickness of the offset spacers easily increase and those in the characteristics of the MOSFETs tend to increase. Since, moreover, etching for forming the offset spacers is performed two times, the amount of etching on the surface of the substrate increases at the time of etching, and the MOS characteristics possibly deteriorate due to loss of implanted impurities. Furthermore, an undesirable excess offset spacer is formed in the MOSFETs in which impurities are ion-implanted first; therefore, the above process is disadvantageous to miniaturization of semiconductor integrated circuits.